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1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50%
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90% of instruction fetch operations are completed in one clock cycle and 10% are completed in 4 clock cycles. On average, access to the data operands of a Load or Store, instruction is completed in 3 clock cycles
On average, instruction fetch takes 0.9+0.1x4 = 1.3 cycles. All instructions, except Load and Store, take four more cycles to complete. Load and Store instructions take two additional cycles, on average. Average completion time = 1.3 + (0.2 + 0.5) x 4 + (0.2 + 0.1) x 6 = 5.9 cycles Instruction rate = 109 /5.9 = 169.5 million instructions per second
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a) Access to the memory is always completed in 1 clock cycle.
Execution rate = 1x109 /5 = 200 million instructions per second
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**Call_register R9 **
• Calls a subroutine whose address is in register R9:
1. Memory address <- [PC], Read memory, IR <-Memory data, PC <-[PC] <- 4
2. Decode instruction, RA <-[R9]
3. PC-Temp<-[PC], PC <-[RA]
4. RY <- [PC-Temp]
5. Register LINK <- [RY]
**Q1: Assume that all memory access operations are completed in one clock** **cycle in a processor that has a 1-GHz clock. What is the frequency of memory access operations if Load and Store instructions constitute 20 percent of the dynamic instruction count in a program? (The dynamic count is the number of instruction executions, including the effect of program loops, which may cause some instructions to be executed more than once.) Assume that all instructions are executed in 5 clock cycles**
There is one memory access to fetch each instruction. Then, 20 percent of the
instructions have a second memory access to read or write a memory
operand. On average, each instruction has 1.2 memory accesses in 5 clock cycles. Therefore, the frequency of memory accesses is (1.2/5) × 10^9
, or 240 million accesses per second.(1 Ghz= 10^9 hz)
** Give the sequence of actions for a Return-from-subroutine instruction in a RISC processor. Assume that the address LINK of the general-purpose register in which the subroutine return address is stored is given in the instruction field connected to address A of the register file (IR31−27).**
Whenever an instruction is loaded into the IR, the contents of the generalpurpose
register whose address is given in bits IR31−27 are read and placed
into register RA. Hence, a Return-from-subroutine instruction will cause the contents of register LINK to be read and placed in register RA.
Execution proceeds as follows:
1. Memory address←[PC], Read memory, Wait for MFC,
IR←Memory data, PC←[PC] + 4 2. Decode instruction, RA←[LINK] 3. PC←[RA] 4. No action 5. No action
**At the time the instruction Load R6, 1000(R9) is fetched, R6 and R9 contain the values 4200 and 85320, respectively. Memory location 86320 contains 75900. **
step 1 and 2: the values are determined by the previous instructions
stept 3: RA = 85320, RB = 4200. Step 4: RA = 85320, RB = 4200, RZ = 86320, RM= 4200. Step 5: RA = 85320, RB = 4200, RZ = 86320, RM= 4200 RY = 75900.
**A block-set-associative cache consists of a total of 64 blocks, divided into 4-block sets. The main memory contains 4096 blocks, each consisting of 32 words. Assuming a 32-bit byte-addressable address space, how many bits are there in each of the Tag, Set, and Word fields?**
Each block contains 128 bytes, thus requiring a 7-bit Word field. There are 16 sets, requiring a 4-bit Set field. The remaining 21 bits of the address constitute the tag field.
Load R2, #A_VEC
Load R3, #B_VEC
Load R4, #3
And R5, R5, R0
LOOP: Load R6, (R2)
Load R7, (R3)
Multiply R6, R6, R7
Add R5, R5, R6
Add R2, R2, #4
Add R3, R3, #4
Subtract R4, #1
Branch>0 LOOP
Load R7, # RESULT
Store R5. (R7)
End
ORIGIN 500
A_VEC: DATAWORD 05, -20, 10
B_VEC: DATAWORD 09, 04, 07
RESULT: RESERVE 4
R2=512, R3=524, R4=0, R5=25 R6=7 R7=524
**Assume that 20% of the dynamic count of the instructions executed for a program are branch instructions. There are no pipeline stalls due to data dependencies. • Static branch prediction is used with a not-taken assumption. a) Determine the execution times for two cases: when 30 percent of the branches are taken, and when 70 percent of the branches are taken. b) Determine the speedup for one case relative to the other. Express the speedup as a percentage relative to 1**
In first case, 30% of branches are taken but we assumed not-taken, so they are mispredicted (one cycle penalty 30% from 20% branch instructions): The value of δbranch_penalty = 0.20 × 0.30 ×1 = 0.06
In second case, 70% of branches are taken but we assumed not-taken, so they are mispredicted (one cycle penalty 70% from 20% branchs): The value of δbranch_penalty = 0.20 × 0.70 ×1 = 0.14
Using S = 1 + δbranch_penalty, the execution time:
in first case is (1.06 × N)/R and (1.14 × N)/R for the second case.
b) Because the execution time for the first case is smaller, the performance improvement as a speedup percentage is:(1.14/1.06 -1)*100=7.5%
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Overflow =cn ⊕ cn−1 or xn−1 yn−1( ̅sn−1) +( ̅xn−1)( ̅yn−1) sn−1
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For the subtraction operation X−Y on 2’s-complement numbers X and Y • We form the 2’s-complement of Y and add it to X . • Set Add/Sub =0 and c0= 0 for addition. • Set Add/Sub =1 and c0 = 1 for subtraction
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4-bit adder has four carry-out signals: c1 = G0 + P0 c0, c2 = G1 + P1G0 + P1P0 c0, c3 = G2 + P2G1 + P2P1G0 + P2P1P0 c0, c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0 c0
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A sequence of n addition cycles generates a 2n-bit product Delay = n * (adder + control delays)
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For n = 32, delay is approximately 32 14 = 448 gate delays
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Registers A and Q are shift registers, together, they hold partial product PPi while multiplier bit qi generates the signal Add/Noadd.At the end of each cycle, C, A, and Q are shifted right one bit position to allow for growth of the partial product as the multiplier is shifted out of register Q
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Cheatography n. The art of mapping complex subjects into clear, instantly navigable reference guides.