CSO Cheat Sheet

A cheat sheet in English by mathildapurr
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Byte ordering of 0x01234567

Byte ordering of 0x01234567

Byte repres­ent­ation of ints

Byte representation of ints

Bit operations (integral data type)

Bit operations (integral data type)

Logical operators

Logical operators

Unsigned integers

Unsigned integers

2's complement

2's complement

2's complement

2's complement

Converting 2's C to decimal

Converting 2's C to decimal

Floating Point Rep

Floating Point Rep

Encoding

Encoding

Precision

Precision

Normalized encoding

Normalized encoding

Normalized encoding example

Normalized encoding example

Denorm­alized encoding

Denormalized encoding

Specia­lized encoding

Specialized encoding

movq operand combo

movq operand combo

Address comput­ation

Address computation

Multip­lic­ation

Multiplication

Division

Division

SetX dest: only set lower 1 byte of register

SetX dest: only set lower 1 byte of register

Jumping

Jumping

2 operand instru­ctions

2 operand instructions

one operand instru­ctions

one operand instructions

useful instru­ction for division

useful instruction for division

Setting condition codes

Setting condition codes

Implicitly setting condition code: addq src, dest

Implicitly setting condition code: addq src, dest

Bad cases for condit­ional move

Bad cases for conditional move

Effect of operations

Logical Operations
CF=0, OF=0
shift
CF=value of last bit shifted out; OF=0
INC, DEC
OF and ZF may change, CF unchanged

Explicitly setting condition codes

cmpl b, a
a-b result not stored anywhere
testq b, a
a&b result not stored anywhere

When are local variables in stack?

Enough registers
No reference to & so no need to go to memory
No arrays, structures

When P(caller) calls Q

When P(caller) calls Q

Structure repres­ent­ation

Structure representation

Procedure data flow

Procedure data flow

Register usage

Register usage

Register usage contd

Register usage contd

Popq dest (for stack)

Popq dest (for stack)

Array access

Array access

Cache structure

Cache structure

Cache calcul­ation

Cache calculation

Cache miss

3 cases
compul­sory, capacity, conflict
How to reduce miss
block size++, associ­ati­vity++, cache size++
Reducing miss penalty
write through (update all) vs write back (update when needed)
 
multilevel cache (optimize hit rate L1, miss rate L2)
Replac­ement policies
LRU, LFU, FIFO, rand

Cache access time

Cache access time

Why Linkers

Why Linkers

Source code to execution

Source code to execution

Resolving symbols

Resolving symbols

Why VM

memory management and protection
permission bits; uses main effici­ent­ly(send unneeded to disk)
Process isolat­ion­/memory protection
own add spaces; can't interfere with anothe­r's memory
loading linking simplified

VP partit­ioned to 3 subsets

Unallo­cated
not yet created, no data, no space
Uncach­ed/­cached
currently cached/not cached

Address transl­ation w page table

Address translation w page table

Page hit

Page hit

page fault

page fault

Speed: TLB hit, mem access-1

Speed: TLB hit, mem access-1

TLB miss (rare with high assoc): 3 mem accesses

TLB miss (rare with high assoc): 3 mem accesses

size-- multilevel page table

size-- multilevel page table

cache and VM

cache uses PA, since with VA, although can be accessed asap, aliasing, 2 VA may map to same block, would not know which one

mem alloc challenges

memory utiliz­ation (sum of malloc­'d data/heap size)
good perfor­mance (mallo­c/free calls return quick)
constr­aints: can't modify malloc­'d memory; can't move malloc­'d block

implicit free list with footer and header

implicit free list with footer and header

explicit free list (pointer don't space+)

explicit free list (pointer don't space+)

Seg list

Seg list

classes of exceptions

classes of exceptions

exception examples

exception examples

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Cheatography n. The art of mapping complex subjects into clear, instantly navigable reference guides.